As technology nodes shrink to 90 nanometers and below, chips become much more difficult to manufacture. In-die process variations increase substantially at 90 nm — even more at 65 nm. If these effects ...

Venice, Florida &@8212 Solido Design Automation has introduced a scalable and extensible solution for meeting design challenges created by process variations at nanometer feature sizes. The new ...

Decision making is a critical step in semiconductor technology development. R&D semiconductor engineers must consider different design and process options early in the development of a next-generation ...

In a recent study done by McKinsey and IDC, we see that physical design and verification costs are increasing exponentially with shrinking transistor sizes. As figure 1 shows, physical design (PD) and ...